Standard system buses, such as ISA (Industry Standard Architecture) and EISA (Extended ISA) buses, are conventionally used in personal computers. Another standard bus, PCI (Peripheral Component Interconnect) bus, is commonly employed in desktop-type personal computers to increase the speed of data transfer and organize system architecture, independently of the kind of processors.
Substantially all data transfer using a PCI bus is block transfer, where each block is transferred by burst transmission. For example, data can be transferred at a transfer speed of 133 megabytes/sec. on a data bus having a width of 32 bits.
Therefore, when a PCI bus is used, data transfer between I/O devices and between a system memory and an I/O device is executed at high speed. As such, system performance is high.
Recently, PCI buses have been used not only in desktop-type personal computers, but also in portable personal computers, such as notebook-type computers.
In desktop type personal computers, option cards for function expansion, such as PCI expansion cards and ISA expansion cards, are directly mounted in an expansion slot on the system board. In such cases, a plurality of pairs of DMA request signal (DREQ) lines and DMA acknowledgment (DACK#) lines corresponding to a plurality of types of DMA channels are defined for each ISA expansion slot to which an ISA expansion card is connected (one pair of lines per slot). As a result, because each ISA expansion card uses a specific DMA channel corresponding to one combination of DREQ and DACK#, the DMA transfer function of a DMAC (direct memory access controller) core on the system board is executed.
Moreover, each PCI expansion slot to which the PCI expansion card is connected (one pair of lines per slot) defines a pair of arbitration control lines composed of a bus access request signal (REQ#) line and a bus access enable signal (GNT#) line. In this case, a PCI bus arbiter on the system board can arbitrate bus accesses of the PCI expansion cards as well as those of PCI devices on the system board.
Consequently, devices that do not require a DMA transfer function, such as PCI bus masters, and devices that do require a DMA transfer function, such as ISA devices, are easily combined in a desktop-type personal computer.
However, even in portable personal computers, it is necessary to mount option cards, such as PCI expansion cards and ISA expansion cards, via an expansion unit known as a desk station. In such a case, it is necessary to reduce as much as possible the number of signal lines leading out from the portable personal computer to the desk station. This is because an increased number of signal lines leading out to the desk station leads to an undesirable increase in the number of pins of the LSI circuit mounted on the system board for interfacing with the desk station, as well as an undesirable increase in the number of pins of the connector for connecting the portable personal computer and the desk station. These increases, in turn, result in an increase in the cost of the portable personal computer and reduction of system mounting efficiency.
As a result, computer systems are not commercially implemented with a plurality of pairs of DMA request signal (DREQ) lines and DMA acknowledgment (DACK#) lines and also a plurality of pairs of bus access request signal (REQ#) line and bus access enable signal (GNT#) lines leading out to the desk station. However, if control lines for DMA transfer are not provided to the desk station, option cards, such as ISA cards, cannot perform DMA transfers. Further the PCI expansion cards cannot serve as a bus master.
A computer system has been recently proposed that utilizes a protocol for transmitting and receiving DMA request signals (DREQ) and DMA acknowledgment (DACK#) signals between an ISA expansion card installed in the desk station and the DMAC core on the system board, and also for transmitting and receiving REQ# and GNT# between a PCI expansion card and the PCI bus arbiter, without using a plurality of pairs of DMA request signal (DREQ) lines and DMA acknowledgment (DACK#) lines and a plurality of pairs of bus access request signal (REQ#) lines and bus access enable signal (GNT#) line.
This protocol uses a pair of signals consisting of a bus access request signal (REQ#) and a bus access enable signal (GNT#) on a PCI bus, to recognize the transferring of DREQ and DACK# between an ISA expansion card and the DMAC core, and also the transferring of REQ# and GNT# between a PCI expansion card and the PCI bus arbiter. Thus, this protocol supports DMA requests (DREQs) for a plurality of channels and requests (REQs#) from PCI bus master in the pair of signals. Hereafter, REQ# and GNT# used for a serial transfer are designated serial REQ# and serial GNT#.
When the above-mentioned DMA serial channel protocol, which serially transfers a plurality of DMA requests and a plurality of PCI bus master requests in this way, is implemented in a bridge interface in the desk station to couple an external PCI bus and an external ISA bus, the bridge interface needs only signal lines corresponding to a PCI bus leading out to the desk station. Hence, it is possible to use both PCI expansion cards and ISA expansion cards.
However, the bridge within the desk station needs a process for serializing DMA request signals (DREQ) of a plurality of channels and PCI bus master request signals (REQs#), and a process for converting in parallel the serialized DREQ channel information transmitted by a serial transfer way in the DMAC core, and inputs the converted information to the ISA expansion cards and the PCI expansion cards in the desk station, with respect to the notification of the DMA acknowledge (DACK#) and the bus access enable signal (GNT#). Therefore, substantial time is required from generation of a DMA request signal (DREQ) and a PCI bus master request signal (REQ#) from the ISA and PCI expansion cards to reception of the DMA request signal and the PCI bus master request signal by the DMAC core and the PCI bus arbiter.
Similarly, the DMAC core needs a process for serializing DACK# signals of a plurality of channels and GNT# signals transmitted by a serial transfer way, and a process for converting in parallel the serialized information transmitted by a serial transfer way to two or more DACK# signals and GNT# signals, and inputs the converted information to the DMAC core and the PCI bus arbiter, with regard to notification of DMA request signals (DREQ) and PCI bus master request signals (REQ#). Therefore, similarly, substantial time is required from generation of a DMA acknowledgment signal (DACK#) and a PCI bus access enable signal (GNT#) from the DMAC core and the PCI bus arbiter to reception of the DMA request signal and the PCI bus master request signal by the ISA and PCI expansion cards, respectively.
The time lag in such serial transfer causes various problems. This is illustrated by the foregoing description of a conventional mechanism receiving transactions from two bus masters that collide due to the transmission delay of the bus access enable signal (GNT#).
(1) A PCI expansion card on an external PCI bus asserts a bus access request signal (REQ#) to request the PCI bus access on an internal PCI bus.
(2) If a bridge in a desk station, coupled to the internal PCI bus and the external PCI bus, receives the REQ#, the bridge transfers the REQ# to a PCI bus arbiter on a system board in a serial transfer way.
(3) The PCI bus arbiter transfers a bus access enable signal (GNT#) corresponding to the bus access request signal (REQ#) to the bridge in a serial transfer way, based on the result of the bus arbitration.
(4) The bridge accesses GNT# out of serial information transferred in a serial transfer way, and transmits it to the PCI expansion card, which is requesting the PCI bus access on the internal PCI bus.
(5) After the PCI expansion card receives GNT# from the bridge, it serves as a bus master to begin the transaction.
(6) When a PCI device on the internal PCI bus, the priority of which is higher than that of the PCI expansion card, asserts a bus access request signal (REQ#) during the execution period of the transaction, the PCI bus arbiter deasserts the bus access enable signal (GNT#) of the PCI expansion card, and transmits it to the bridge in a serial transfer way. The PCI bus arbiter asserts a bus access enable signal (GNT#) of the PCI device with high priority active.
(7) The bridge accesses the information that shows inactive GNT# from serial information transferred in a serial transfer way, and transmits it to the PCI expansion card. When the PCI expansion card recognizes that the GNT# is deasserted, it processes a present cycle of the transaction as the final cycle.
(8) On the other hand, the PCI device on the internal PCI bus, the GNT# of which a PCI device is asserted, begins the operation as a bus master. At this time, if the access of the PCI device is a target on the external PCI bus, the transaction executed by the PCI device is sent to the external PCI bus by way of the bridge.
(9) As mentioned above, the serial transfer of GNT# requires a lot time for a delay by the processing of the parallel-serial conversion and the serial-parallel conversion. Hence, the transaction of the PCI device on the internal PCI bus is transmitted to the external PCI bus by way of the bridge before the PCI expansion card ends the operation as a bus master.
(10) In this case, there is a collision between the transaction executed by the PCI expansion card and the transaction executed by a PCI device of which GNT# is newly asserted. The bridge cannot respond to the transaction from the PCI device of which GNT# is newly asserted until the transaction of the PCI expansion card ends. Therefore, the PCI device that began the transaction determines that there is not a target on the external PCI bus. This causes a master abort. If a master abort occurs at this time, the same transaction executed by the PCI device is not reexecuted.
Therefore, the conventional computer system, to which the DMA serial channel protocol is applied, contains a delay in the GNT# transmission to the PCI expansion card. Thus, the situation results in the transactions colliding.